The present invention relates generally to hardware testing and, more particularly, to automatic at-speed fault-testing of logic blocks using logic-BIST (Built-In Self Test) circuits.
Testing of digital logic blocks is commonly performed using automatic testing equipment (ATE) and scan-chains in the digital logic block. Although this approach works, the tests are performed at speeds that are slower than the intended operational speed of the digital logic block under test. Thus, logic which fails at-speed or at desired speeds but passes at low speeds is not detected. In addition, such tests generally do not test the macros interface to the digital logic. Hence, since the interfaces between macros and logic are generally tested individually, failures of the connectivity may not be detected. Furthermore, a complex ATE interface does not allow for convenient testing of a chip in the field by a field engineer.
Accordingly, a system and method is needed for at-speed testing of an entire logic block using a simple ATE interface.